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features ? fast read access time ? 70 ns automatic page write operation ? internal address and data latches for 64 bytes fast write cycle times ? page write cycle time: 2 ms maximum (standard) ? 1 to 64-byte page write operation low power dissipation ? 40 ma active current ? 100 a cmos standby current hardware and software data protection data polling and toggle bit for end of write detection high reliability cmos technology ? endurance: 100,000 cycles ? data retention: 10 years single 5 v 10% supply cmos and ttl compatible inputs and outputs jedec approved byte-wide pinout industrial temperature ranges green (pb/halide-free) packaging 1. description the at28hc64bf is a high-performance electrically-erasable and programmable read-only memory (eeprom). its 64k of me mory is organized as 8,192 words by 8 bits. manufactured with atmel?s advanced non volatile cmos technology, the device offers access times to 55 ns with power dissipation of just 220 mw. when the device is deselected, the cmos standby current is less than 100 a. the at28hc64bf is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. during a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a writ e cycle, the device will automatically write the latched data using an internal control timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected, a new access for a read or write can begin. atmel?s at28hc64bf has additional features to ensure high quality and manufactura- bility. the device utilizes internal erro r correction for extended endurance and improved data retention characteristics. an optional software data protection mecha- nism is available to guard against inadvert ent writes. the device also includes an extra 64 bytes of eeprom for device identification or tracking. 64k (8k x 8) high speed parallel eeprom with page write and software data protection at28hc64bf 3648a?peepr?10/06
2 3648a?peepr?10/06 at28hc64bf 2. pin configurations 2.1 28-lead pdip/soic top view pin name function a0 - a12 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect dc don?t connect 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we nc a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 2.2 32-lead plcc top view note: plcc package pins 1 and 17 are don?t connect. 2.3 28-lead tsop top view 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a6 a5 a4 a3 a2 a1 a0 nc i/o0 a8 a9 a11 nc oe a10 ce i/o7 i/o6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd dc i/o3 i/o4 i/o5 a7 a12 nc dc vcc we nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 oe a11 a9 a8 nc we vcc nc a12 a7 a6 a5 a4 a3 a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2
3 3648a?peepr?10/06 at28hc64bf 3. block diagram 4. device operation 4.1 read the at28hc64bf is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the out- puts. the outputs are put in the high-impedance state when either ce or oe is high. this dual line control gives designers flexibility in pr eventing bus contention in their systems. 4.2 byte write a low pulse on the we or ce input with ce or we low (respectively) and oe high initiates a write cycle. the address is latc hed on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . once a byte write has been started, it will automatically time itself to completion. once a programming operation has been initiated and for the duration of t wc , a read operation will effect ively be a polling operation. 4.3 page write the page write operation of the at28hc64bf allows 1 to 64 bytes of data to be written into the device during a single internal programming period. a page write operation is initiated in the same manner as a byte write; after the first by te is written, it can then be followed by 1 to 63 additional bytes. each successive byte must be loaded within 150 s (t blc ) of the previous byte. if the t blc limit is exceeded, the at28hc64bf w ill cease accepting data and commence the internal programming operation. all bytes duri ng a page write operation must reside on the same page as defined by the state of the a6 to a12 inputs. for each we high-to-low transition during the page write operation, a6 to a12 must be the same. the a0 to a5 inputs specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be written; unnecessa ry cycling of other bytes within the page does not occur. 4.4 data polling the at28hc64bf features data polling to indicate the end of a write cycle. during a byte or page write cycle, an attempted re ad of the last byte written will result in the complement of the written data to be presented on i/o7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at any time during the write cycle. vcc gnd oe we ce address inputs x decoder y decoder oe, ce and we logic data inputs/outputs i/o0 - i/o7 data latch input/output buffers y-gating cell matrix identification
4 3648a?peepr?10/06 at28hc64bf 4.5 toggle bit in addition to data polling, the at28hc64bf provides another method for determining the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the write has completed, i/o6 will stop toggling, and va lid data will be read. toggle bit re ading may begin at any time during the write cycle. 4.6 data protection if precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. atmel ? has incorporated both hardware and software features that will protect the memory against inadvertent writes. 4.6.1 hardware protection hardware features protect against inadvertent writes to the at28hc64bf in the following ways: (a) v cc sense ? if v cc is below 3.8 v (typical), the wr ite function is inhibited; (b) v cc power-on delay ? once v cc has reached 3.8 v, the device will automatically time out 5 ms (typical) before allowing a write; (c) write inhibit ? holding any one of oe low, ce high or we high inhibits write cycles; and (d) noise filter ? pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a write cycle. 4.6.2 software data protection a software-controlled data protection feature has been implemented on the at28hc64bf. when enabled, the software data protection (sdp), will prevent inadvertent writes. the sdp feature may be enabled or disabled by the user; the at28hc64bf is shipped from atmel with sdp disabled. sdp is enabled by the user issuing a series of three write commands in which three specific bytes of data are written to three specific addresses (refer to the ?software data protection algorithm? diagram on page 10 ). after writing the 3-byte command sequence and waiting t wc , the entire at28hc64bf will be protected against inadvertent writes. it should be noted that even after sdp is enabled, the user may still perform a byte or page write to the at28hc64bf. this is done by preceding the data to be written by the same 3-byte command sequence used to enable sdp. once set, sdp remains active unless the disable command sequence is issued. power transi- tions do not disable sdp, and sdp protects the at28hc64bf during power-up and power- down conditions. all command sequences must conform to the page write timing specifica- tions. the data in the enable and disable command sequences is not actually written into the device; their addresses may still be written with user data in either a byte or page write operation. after setting sdp, any attempt to write to the device without the 3-byte command sequence will start the internal write time rs. no data will be written to the device, howeve r. for the dura- tion of t wc , read operations will effectively be polling operations. 4.7 device identification an extra 64 bytes of eeprom me mory are available to the user for device identification. by raising a9 to 12 v 0.5 v and using address locations 1fc0h to 1fffh, the additional bytes may be written to or read from in the same manner as the regular memory array.
5 3648a?peepr?10/06 at28hc64bf notes: 1. x can be vil or vih. 2. see ?ac write waveforms? on page 8. 3. vh = 12.0 v 0.5 v. 5. dc and ac operating range at28hc64bf-70 at28hc64bf-90 at28hc64bf-120 operating temperature (case) -40c - 85c -40c - 85c -40c - 85c v cc power supply 5 v 10% 5 v 10% 5 v 10% 6. operating modes mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z chip erase v il v h (3) v il high z 7. absolute maximum ratings* temperature under bias................................ -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability storage temperature ..................................... -65c to +150c all input voltages (including nc pins) with respect to ground .................................-0.6 v to +6.25 v all output voltages with respect to ground ...........................-0.6 v to v cc + 0.6 v voltage on oe and a9 with respect to ground ..................................-0.6 v to +13.5v 8. dc characteristics symbol parameter condition min max units i li input load current v in = 0 v to v cc + 1 v 10 a i lo output leakage current v i/o = 0 v to v cc 10 a i sb1 v cc standby current cmos ce = v cc - 0.3 v to v cc + 1 v 100 a i sb2 v cc standby current ttl ce = 2.0 v to v cc + 1 v 2 ma i cc v cc active current f = 5 mhz; i out = 0 ma 40 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.40 v v oh output high voltage i oh = -400 a 2.4 v
6 3648a?peepr?10/06 at28hc64bf 10. ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. 9. ac read characteristics symbol parameter at28hc64bf-70 at28hc64bf-90 at28hc64bf-120 units min max min max min max t acc address to output delay 70 90 120 ns t ce (1) ce to output delay 70 90 120 ns t oe (2) oe to output delay 0 35 0 40 0 50 ns t df (3)(4) oe to output float 035040050ns t oh output hold 0 0 0 ns t ce t oe t acc t df t oh oe ce address output output valid address valid high z
7 3648a?peepr?10/06 at28hc64bf 11. input test waveforms and measurement level 12. output test load note: 1. this parameter is characterized and is not 100% tested. t r , t f < 5 ns 13. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 46pfv in = 0 v c out 812pfv out = 0 v
8 3648a?peepr?10/06 at28hc64bf 15. ac write waveforms 15.1 we controlled 15.2 ce controlled 14. ac write characteristics symbol parameter min max units t as , t oes address, oe setup time 0 ns t ah address hold time 50 ns t cs chip select setup time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )100ns t ds data setup time 50 ns t dh , t oeh data, oe hold time 0 ns oe we ce address data i n t cs t oes t as t dh t oeh t ah t wp t ds t ch oe we ce address data i n t cs t oes t as t dh t oeh t ah t wp t ds t ch
9 3648a?peepr?10/06 at28hc64bf 17. page mode write waveforms (1)(2) notes: 1. a6 through a12 must specify the same page address during each high to low transition of we (or ce ). 2. oe must be high only when we and ce are both low. 18. chip erase waveforms t s = t h = 5 s (min.) t w = 10 ms (min.) v h = 12.0 v 0.5 v 16. page mode characteristics symbol parameter min max units t wc write cycle time 2ms t as address setup time 0 ns t ah address hold time 50 ns t ds data setup time 50 ns t dh data hold time 0 ns t wp write pulse width 100 ns t blc byte load cycle time 150 s t wph write pulse width high 50 ns oe we ce a0 -a12 data t as valid add valid data t ah t ds t wp t wph t dh t blc t wc t s t w t h
10 3648a?peepr?10/06 at28hc64bf 19. software data protection enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a12 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data are loaded. load data aa to address 1555 load data 55 to address 0aaa load data a0 to address 1555 load data xx to any address (4) load last byte to last address enter data protect state writes enabled (2) 20. software data protection disable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a12 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data are loaded. load data aa to address 1555 load data 55 to address 0aaa load data 80 to address 1555 load data aa to address 1555 load data 20 to address 1555 load data xx to any address (4) load last byte to last address load data 55 to address 0aaa exit data protect state (3) 21. software protected write cycle waveforms (1)(2) notes: 1. a6 through a12 must specify the same page address during each high to low transition of we (or ce ) after the software code has been entered. 2. oe must be high only when we and ce are both low. oe we ce a6 - a12 data a0 -a5 t as t ah t ds t dh t wp t wph t blc t wc
11 3648a?peepr?10/06 at28hc64bf note: 1. these parameters are characterized and not 100% tested. see ?ac read characteristics? on page 6. 23. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see ?ac read characteristics? on page 6. 25. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used, but the address should not vary. 22. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 0 ns t oeh oe hold time 0 ns t oe oe to output delay (1) ns t wr write recovery time 0 ns 24. toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns t dh t oe t oeh t wr t dh t wr t oe t oeh (2)
12 3648a?peepr?10/06 at28hc64bf 26. normalized i cc graphs
13 3648a?peepr?10/06 at28hc64bf 27. ordering information 27.1 green package (pb/halide-free) t acc (ns) i cc (ma) ordering code package operation range active standby 70 40 0.1 at28hc64bf-70ju at28hc64bf-70pu at28hc64bf-70su at28hc64bf-70tu 32j 28p6 28s 28t industrial (-40 c to 85 c) 90 40 0.1 AT28HC64BF-90JU at28hc64bf-90pu at28hc64bf-90su at28hc64bf-90tu 32j 28p6 28s 28t 120 40 0.1 at28hc64bf-12ju at28hc64bf-12pu at28hc64bf-12su at28hc64bf-12tu 32j 28p6 28s 28t package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 28p6 28-lead, 0.600" wide, plastic dual inline package (pdip) 28s 28-lead, 0.300" wide, plastic gull wing small outline (soic) 28t 28-lead, plastic thin small outline package (tsop) 28. valid part numbers the following table lists standard atmel products that can be ordered. device numbers speed package and temperature combinations at28hc64bf 70 ju, pu, su, tu at28hc64bf 90 ju, pu, su, tu at28hc64bf 12 ju, pu, su, tu 29. die products reference section: parallel eeprom die products
14 3648a?peepr?10/06 at28hc64bf 30. packaging information 30.1 32j ? plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 3.175 ? 3.556 a1 1.524 ? 2.413 a2 0.381 ? ? d 12.319 ? 12.573 d1 11.354 ? 11.506 note 2 d2 9.906 ? 10.922 e 14.859 ? 15.113 e1 13.894 ? 14.046 note 2 e2 12.471 ? 13.487 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ
15 3648a?peepr?10/06 at28hc64bf 30.2 28p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28p6 , 28-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 28p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.826 a1 0.381 ? ? d 36.703 ? 37.338 note 2 e 15.240 ? 15.875 e1 13.462 ? 13.970 note 2 b 0.356 ? 0.559 b1 1.041 ? 1.651 l 3.048 ? 3.556 c 0.203 ? 0.381 eb 15.494 ? 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ab. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
16 3648a?peepr?10/06 at28hc64bf 30.3 28s ? soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28s , 28-lead, 0.300" body, plastic gull wing small outline (soic) jedec standard ms-013 b 28s 8/4/03 dimensions in millimeters and (inches). controlling dimension: millimeters. top view side views 0.51(0.020) 0.33(0.013) 7.60(0.2992) 7.40(0.2914) 10.65(0.419) 10.00(0.394) 1.27(0.50) bsc 2.65(0.1043) 2.35(0.0926) 18.10(0.7125) 17.70(0.6969) 0.30(0.0118) 0.10(0.0040) 0.32(0.0125) 0.23(0.0091) 1.27(0.050) 0.40(0.016) 0o ~ 8o pin 1
17 3648a?peepr?10/06 at28hc64bf 30.4 28t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28t , 28-lead (8 x 13.4 mm) plastic thin small outline package, type i (tsop) c 28t 12/06/02 pin 1 0o ~ 5o d1 d pin 1 identifier area b e e a a1 a2 c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-183. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.90 1.00 1.05 d 13.20 13.40 13.60 d1 11.70 11.80 11.90 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.55 basic
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